Flash EPROM devices, commonly referred to as flash memory devices, typically include at least one memory array organized into rows and columns of flash memory cells. The array is typically partitioned into blocks, each of which is further divided into sectors. A row decoder and a column decoder are used to select a single row and at least one column of memory cells based upon an address applied to the flash memory device. Sense amplifiers are coupled to column lines corresponding to the columns of memory cells to amplify the voltage levels on the addressed column lines corresponding to the data values stored in the addressed flash memory cells. The particular implementations of known arrays and row/column decoders will not be discussed further herein.
Flash memory devices typically are capable of performing write operations whereby data can be “written to” (i.e., programmed to or erased from) memory cells selected by a write address applied to the row/column decoders during a write operation in the flash memory device. A read operation can be used to retrieve data previously written to memory cells selected by a read address applied to the row/column decoders during a read operation in the flash memory device.
Because write operations in a flash memory device typically take more time to perform than read operations, flash memory devices have been implemented as multi-bank structures so that a read operation can be performed in one of the banks while a write operation is simultaneously performed in another bank, which can provide a performance improvement over non-multi-bank structures. This type of multi-bank structure is sometimes referred to as “read-while-write” capability.
FIG. 1 is a block diagram illustrating a conventional multi-bank flash memory device 100 having read-while-write capability. In particular, the flash memory device 100 includes a plurality of banks of flash memory 110A–110C each of which is partitioned into multiple sectors. For example, the bank 110A is partitioned into sectors 115a–e, bank 110B is partitioned into sectors 115f–j, and the bank 110C is partitioned into sectors 115k–o. Each of the sectors 115 of the flash memory device 100 has an associated local decoder circuit 105. Each of the local decoder circuits 105 is coupled to the associated sector 115 via a plurality of word lines that can be used to access memory cells located within the sector 115.
The local decoder circuits 105 are activated responsive to address signals provided thereto that indicate which memory cells in the memory are to be accessed. For example, the address signals provided to the local decoder circuits 105 can indicate which of the banks 110A–110C, and which of the sectors 115a–o, and which of the plurality word lines corresponding to the memory cells identified by the address signals are to be accessed during a memory read or write operation. As discussed above, the multi-bank device 100 is capable of performing a read or write operation in one of the banks while another read or write operation is conducted in another bank simultaneously. For example, a write operation may be performed to memory cells in sector 115a while a read operation is simultaneously carried out in sector 115o. 
FIG. 2 is a schematic diagram illustrating the local decoder circuit 105 shown in FIG. 1. The local decoder circuit 105 includes a combinatorial logic circuit 210 that further includes a NAND gate 201 that receives selected ones of the address signals that indicate which memory cells are to be accessed during a read or write operation. This is sometimes referred to as “decoding the address.”
If the address signals provided to the combinatorial logic circuit 210 decodes to memory cells included in the sector associated with the local decoder circuit 105, the word line drive signal WL DRV coupled to a word line driver circuit 220 is pulled low when a select signal is asserted. The word line driver circuit 220 activates one of the word lines WL<7:0> based on a plurality of word line select signals PWL<7:0>. A decoder Enable signal can be used to provide a supply voltage VPX to the word line drive signal prior to or subsequent to a memory operation as a reset.
The word line select signals PWL<7:0> can be provided to the local decoder circuit 105 with the address signals, wherein one of the word line select signals PWL<7:0> is activated and the remainder of the word line select signals PWL<7:0> are deactivated. The portion of the word line driver circuit 220 that is responsive to the activated word line select signal PWL<7:0> activates the word line WL<7:0> that is coupled thereto. The local decoder circuit 105 also includes a reset circuit 230 that can insure that the remaining word lines WL (i.e., the word lines that are not selected) remain in the off state. The read or write operation can thereby be carried out to addresses memory cells.
Address decoding for flash memory devices is also discussed in U.S. Pat. No. 6,064,623 to Ha, and in U.S. Pat. No. 6,240,040 to Akaogi et al., and in U.S. Pat. No. 6,256,262 to Chen et al., the entire disclosures of which are hereby incorporated herein by reference in their entireties.